1. Field of the Invention
The present invention relates to a Gate In Panel (GIP) type liquid crystal display (LCD) device, and more particularly to an electrostatic protection circuit for signal lines of an LCD device.
2. Discussion of the Related Art
A liquid crystal display (LCD) device uses an electric field to control the light transmittance through liquid crystal having dielectric anisotropy to thereby display images. The typical LCD device includes an LCD panel including a plurality of pixel regions arranged in a matrix configuration, and a driving circuit that drives the LCD panel.
The LCD panel includes first and second substrates bonded to each other with a predetermined interval therebetween, and a liquid crystal layer formed between the first and second substrates. The first substrate includes a plurality of substantially perpendicular gate and data lines that cross to define the pixel regions; a pixel electrode formed in each pixel region; and a thin film transistor formed adjacent to a crossing of the gate and data lines. The thin film transistor is turned-on in response to a scan signal applied sequentially to each gate line to apply a data signal from the data line to the corresponding pixel electrode.
The second substrate includes a black matrix layer that prevents light leakage through portions of the LCD panel other than the pixel region; a color filter layer formed in each pixel region for rendering colors; and a common electrode formed in correspondence with the pixel electrode to drive the liquid crystal layer.
The driving circuit includes a gate driver for driving the gate lines; a data driver for driving the data lines; and a timing controller for supplying a data signal and a control signal to control the gate driver and the data driver.
The gate driver includes a shift register that sequentially outputs a scan pulse to each gate line. The shift register is provided with a plurality of stages connected in sequence. The plurality of stages output the scan pulse sequentially to scan the gate lines of the LCD panel sequence.
In particular, the first stage receives a start pulse from the timing controller as a trigger signal, and each of the other stages receives a signal output from a prior stage as a trigger signal. In other words, at least one of a plurality of clock pulses of differing phase is applied to each stage in sequence. Accordingly, a scan pulse is sequentially output from the first to the last stages.
A gate driver of the related art may be implemented using a gate driver IC including the shift register and connected to a gate line pad of the LCD panel using a tape carrier package (TCP).
The data driver is typically implemented using a data driver IC. However, the gate driver may be implemented using GIP (Gate In Panel) technology in which a shift register is formed on an LCD panel to decrease material costs, manufacturing process steps, and fabrication time.
Hereinafter, a related art GIP type LCD device will be described with reference to FIGS. 1 and 2 of the accompanying drawings.
FIG. 1 is a plan view of a related art GIP type LCD device. FIG. 2 is an expanded plan view of an electrostatic protection circuit of FIG. 1.
In the related art GIP type LCD device, as shown in FIG. 1, a lower substrate 1 is bonded to an upper substrate 2 by a sealant 9 with the lower substrate 1 separated from the upper substrate 2 by a predetermined interval or cell gap. The lower substrate 1 is larger than the upper substrate 2, as the lower substrate 1 includes a non-display area in which a data driver is mounted. The display area of the LCD panel is provided in the region inside the sealant 9 between the bonded the lower and upper substrates 1 and 2. A TCP 7 is mounted in the non-display area of the lower substrate 1. A common line formed on the lower substrate may be electrically connected to a common electrode on the upper substrate via a conductive sealant rather than by using silver (Ag) dots.
The display area of the lower and upper substrates 1 and 2 is divided into an active region (A/A) and a dummy region (D).
The active region (A/A) of the display area on the lower substrate 1 is provided with pixel regions defined by crossings of a plurality of gate lines and a plurality of data lines. Each pixel region includes a pixel electrode and a thin film transistor. Additionally, the active region (A/A) of the display area on the upper substrate 2 is provided with a black matrix layer, a color filter layer, and a common electrode.
The dummy region (D) of the display area on the lower substrate 1 includes a common line (not shown), a GIP gate driver 3, a GIP dummy gate driver 4, and signal lines 5 for applying various signals (clock signal, enable signal, start signal, common voltage, and etc.) output from the timing controller to the GIP gate driver 3 and the GIP dummy gate driver 4. The dummy region (D) of the display area on the upper substrate 2 is provided with a black matrix layer.
A liquid crystal layer is formed in the display area between the lower and upper substrates 1 and 2.
If an electrostatic charge is applied to the signal lines 5 during the manufacturing process, elements of the internal circuitry may damaged. An electrostatic protection circuit is provided with the signal lines 5 to prevent damage to internal circuit elements of the inner circuit from being damaged.
The electrostatic protection circuit 6 will be explained with reference to FIG. 2.
The electrostatic protection circuit 6 is formed in the dummy region at the upper left corner of the LCD panel. The electrostatic protection circuit 6 is formed on a first gate line (for example, the dummy gate line). More particularly, the dummy region includes additional lines 8 corresponding to each signal line connected between the first gate line of the active region and each signal line 5. Electrostatic protection elements 6a corresponding to the number of signal lines are provided in each line 8.
However, the related art GIP type LCD device has the following disadvantages.
In the related art GIP type LCD device, the sealant does not overlap with the electrostatic protection circuit. The electrostatic protection circuit for the signal lines is formed in the dummy region at the upper left side of the LCD panel in which the first gate line is formed. Accordingly, as the electrostatic protection circuit approaches the sealant for bonding the lower and upper substrates, the area available for sealant formation is decreased introducing processing difficulties.
Additionally if the electrostatic protection circuit is formed close to the sealant for bonding the lower and upper substrates and the sealant is formed of the conductive material, the signal lines and the common electrode of the upper substrate may be shorted together.